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S.S.H.I.S.H.I.V. 1: ICE "IHBM" for the release by SK Hercules of the thermodistant storage technology "iHBM": ICLE" for encapsulating integrated cooling elements

KK Hercules announced the launch of the iHBM technology. It significantly reduces the heat at the time of operation of the product by integrating the integrated cooling component “ICE” in HBM seals.

As the demand for al-calculations continues to surge, HBM continues to upgrade its performance over time by increasing the number of stacks and increasing the speed of operation, while also posing the challenge of heating up. Effective control of connection between HBM andGPUThe power density of the D2D PHY region is at the core of the next generation of HBM technology competitiveness.

The iHBM technology is characterized by a fundamental structural solution to the dissipation problem described above. The iHBM directly embeds thermal control component (ICE) in the D2D PHY area, where the concentration of heat is most concentrated, and constructs the Specialized Heat Ejection Channel (Heat Path), replacing the traditional HBM-dependent indirect heat dispersion method, which is transmitted externally via Core Die. Compared to traditional programmes, iHBM reduces thermal resistance by more than 30 per cent and ensures the stable operation of products in high temperature and load environments.

The introduction of a fully market-tested advanced MR-MUF4 crystal-type (WLP) sealing process has also given the iHBM technology a significant advantage in terms of the feasibility of production and the ability to achieve a stable scale of production. The iHBM technology is also highly designed to be compatible with the client ' s existing system-level encapsulation (SiP) environment and can be deployed directly without large-scale modifications to the design, thus lowering the import threshold.

KK Hercules plans to apply iHBM technology to next-generation products such as HBM5 to meet the stringent heat control needs of ultra-high-integral, high-bandwidth applications such as high-performance computing (HPC), AID data centres and to further improve the stability and operational efficiency of the overall system.

Original link: https://www.expreview.com/106052.html

With the increased demand for HBM memory capacity and performance from the AI chip, the HBM memory high temperature problem was in fact pre-empted. Rather than relying on external radiators, why can't there be an in-house chip-level solution? The "iHBM" technology is here. This magical ICE component looks very small, and it's only a small part of the HBM memory, and it's not clear what black technology SK Hercules has in mind. But there must be a price to this beautiful thing, a higher demand for the baseboard, a lower probability, and no idea what Hercules would weigh.

News 2: A DDR5 RAM with a Turbo fan co-sponsored by Cold-To-Hand and Chic: MasterDimm AC

It's not unusual to have a self-contained active radiator, and some high-end holograms do send down a pressurized fan heater, but I've never seen a turbo fan directly on the RAM. MasterDimm AC, a DDR5 memory with a turbo fan radiator, was jointly released by Cold-Sweet and Chic, and will be displayed during the Taipei computer exhibition this year.

The MasterDimm AC-series memory provides up to 64GB*2 packages, providing AMD EXPO and Intel XMP 3.0 versions, of which the EXPO version provides up to 6,000MT/s CL26 low-delayed configurations, while the XMP version uses high-frequency CUDIM, up to 8,400MT/s.

MasterDimm AC uses noise-optimised turbine fans and specially designed air-flow heat sheets to achieve better dissipation at noise levels below 35 dB. The MasterDimm AC, which is equipped with an active radiator, can provide a reduced memory working temperature of 15°C.

Of course, it is not realistic to want a turbine fan on the width of a conventional memory, and MasterDimm AC actually occupies the space of two memory slots, so they can only be used on the main panel of the four slots, which are very common for double slots, and for the first time. Of course, MasterDimm AC's maximum 128GB capacity actually meets most users' demand for memory capacity.

Original link: https://www.expreview.com/106143.html

Not without a chip-level solution? Not really. Although not as hot as HBM in the AI chip, the high temperature of the home-based DDT5 memory has been a common issue since its inception. For its part, Chi Chi Chi cooperated across borders with the cold-hot-hot plant, and turbo-dispers were used in memory products. There's a lot of active dissipation, but the vortex has never seen it, and it's just thickening to the "twin" thickness... ... using future expansion and maximum capacity caps in exchange for lower temperatures, more stable working conditions, greater performance release and higher ultra-frequency potential, don't you know if it's worth it?

News 3: Energy efficiency of an energy builder is becoming a priority for the AI chip, more important than computing capacity

The energy efficiency of the chips has received increased attention over the past few years, and is a major constraint to future chip development, as the amount of computing generated by artificial intelligence (AI) has risen dramatically. Many of the technologies that would have been used only for mobile devices, with better energy efficiency performance, are now being used more in data centre-related products, such as LPDDR memory.

According to TrendForce, in public, the recent build-up of station power indicates that clients are increasingly focusing on performance improvements that minimize additional energy consumption, from smartphone manufacturers to AI data centre operators. This change is also reflected in the process technology for the generation of power from stations, which is expected to increase performance by more than 20 per cent compared to the N2 process in the upcoming A14 process and reduce power consumption by 30 per cent.

A14 will introduce the second-generation GAA transistor and further increase flexibility through NanoFlex Pro, with test production expected by the end of 2027 and volume production by 2028. However, the initial A14 process does not support super-track (Super Power Railway, SPR) structures, i.e., back-to-back power supply technology, which will bring back-to-back power in 2029 to meet high-performance client and data centre applications.

While the increase in transistor density remains at the heart of the road map for the development of particle power, advanced seals, chip stacks and photon technologies are becoming increasingly important in driving efficiency gains. Energy efficiency improvement has become a more urgent priority for the next generation of AI chips than a continuous reduction in the size of transistors in terms of the A13 and A12 processes of the power generation planning.

Original link: https://www.expreview.com/106135.html

When attention is being paid to temperature issues, the importance of bottom-up manufacturing processes is also highlighted by the outpouring of power. In the foreseeable future, energy efficiency will become a more important priority than performance, and the decline in power consumption is an important point of improvement in future manufacturing processes. Looks like there's a lot of heat-dispersion programs in the front, and sometimes it's better to upgrade the PET process, which is the price of the PET.

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