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UNDAC STATES THAT THE NEXT GENERATION OF CHIPS WILL BE EXCLUSIVE IN INTEL EMIB-T SEALING, EXPECTED 2027 Q4 MASS PRODUCTION

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IT House News, 2 June, at the Goldman Sachs Day event held during COMPUTEX 2026, UNDG announced that its next generation of chips would use only the Intel EMIB-T advanced containment technology and no longer use the CoWos programme.

During the meeting, the United Nations Development Programme (UNDP) disclosed that the next generation of chips (tape-out) target was scheduled for the fourth quarter of 2026 and that it planned to enter the production phase in the fourth quarter of 2027.

According to Goldman Sachs, the business progress at the Enterprise level of UNDGC has exceeded expectations, and the complexity of the design of secondary chips has increased significantly, with the full implementation of advanced containment techniques such as EMIB-T, which is expected to produce this year ' s Q4 sample and the fourth quarter of 2027. Although it is not clear which chips are specifically covered by the project, there is a general perception within the industry that customization of AI chips and CPUs will be involved.

Intel has positioned EMIB as a direct competition for desk power, CoWos. There is a significant difference in the technical path between the two: CoWoS uses large-scale silicon mediar (interposer) to connect different components, while EMIB selectively connects GPU core and memory components through embedded silicon bridge.

Intel claims that the design of removing the intermediate layer can reduce manufacturing complexity and overall costs. In addition to ICD, the next generation of Google's TPU custom AI chip is also assessing the possibility of encapsulating with EMB-T.

Guo Ming Jing noted that Intel had set 98 per cent of the positive rate as the benchmark for the EMIB-T process, with the aim of making it comparable to the FCBGA process. Google will also pay close attention to the positive performance of EMIB-T, because it is directly related to its cost advantage in competing with Inverda -- a higher positive rate means that more chips are available per batch, thus reducing the cost of producing a single chip. According to previous supply chain reports, the current validation rate for the advanced encapsulation of Intel EMIB-T is about 90 per cent, but there is still a significant gap between the production standards of 98 per cent and the difficulty of crossing from 90 per cent to 98 per cent is considered to be much greater than the phase from zero.

At the same time, the decision of the United Nations Development Programme had a ripple effect at the supply chain level. According to the Business Times of Taiwan, China, the two producers of Epp and Liquor have confirmed their entry into the Intel EMIB-T sealed supply chain and, together with IDB, into the Google Generation TPU project. Prior to this, the cylindrical capacitor products of cylindrical technology were said to have played a key role in the IA chip project designed for Google by IDB. IT House has also previously reported that the TPU v9x "Humu Fish" reasoning chip project developed by UNDAC for Google uses EMIB-T technology in Intel.

It is noteworthy that Google has also shown a positive cost-control stance in this re-enactment strategy. According to supply chain sources, Google is trying to cut the mark-up cost of the intermediate by bypassing UNDC and purchasing Humufish crystal round directly from the desk. This move reflects a shift in Google from a relatively relaxed procurement strategy in the past to a well-calculated cost controller, with the intention of building a cost advantage in competition for the AI chip in British Wida.

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UNDAC STATES THAT THE NEXT GENERATION OF CHIPS WILL BE EXCLUSIVE IN INTEL EMIB-T SEALING, EXPECTED 2027 Q4 MASS PRODUCTION | aimode.news